Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions

ABSTRACT

An efficient method and computer program for modeling and improving stating memory performance across process variations and environmental conditions provides a mechanism for raising the performance of memory arrays beyond present levels/yields. Statistical (Monte-Carlo) analyses of subsets of circuit parameters are performed for each of several memory performance variables and then sensitivities of each performance variable to 15 each of the circuit parameters are determined. The memory cell design parameters and/or operating conditions of the memory cells are then adjusted in conformity with the sensitivities, resulting in improved memory yield and/or performance. Once a performance level is attained, the sensitivities can then be used to alter the probability distributions of the performance variables to achieve a higher yield. Multiple cell designs can be compared for performance, yield and sensitivity of performance variables to circuit parameters over particular environmental conditions in order to select the best cell design.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to memory circuit designmethodologies and programs for designing digital memory circuits, andmore particularly to a method and computer program for improving staticmemory performance across process variations and environmentalconditions.

2. Description of the Related Art

Memory speed and other performance factors are critical limitations intoday's processing systems and are predicted to become even more of acritical limitation as technologies move forward. In particular, staticrandom access memories (SRAMS) and memory cells are used in processorcaches, registers and in some designs external to the system processorsfor fast access to data and program instructions.

With processor cycle frequencies reaching well above 4 Ghz, developmentof SRAM cells that can store and provide access to stored values withinthat period has become necessary. However, at process scales necessaryto achieve such access are also increasingly subject to variability incircuit parameters such as device threshold voltages and channeldimensions. Charge history effect and physical nano-scale effects due tonon-ideal materials also come increasingly into place as device size isdecreased.

Semiconductor memories in general are also becoming the predominantpower consumer in almost every processing system and particularly inprocessors, cache memory is a major consumer of power. As such,reduction of SRAM cell power supply voltages is highly desirable, aspower dissipation and overall power requirements are dictated by thesupply voltages used. However, lower supply voltages typical dictatelower performance levels in terms of cell read and write stability andaccess delay.

Because of all of the above-described limitations, yield reduction dueto SRAM cell variability or increased redundancy requirements willincrease production cost and waste or limit available space and designflexibility in order to provide sufficient redundancy to maintainyields.

Present analysis techniques require large amounts of processing power toextend an accurate yield/performance analysis beyond three standarddeviations (3σ) of device parameter variations. However, if it werepractical to perform more extensive analyses and further if a techniquefor determining which design parameters can be efficaciously alteredwere provided, memory device designs could be improved beyond presentlevels and designs for much higher operating frequencies could begenerated.

It is therefore desirable to provide a method for modeling and improvingSRAM cell performance across process variations and environmentaloperating conditions in an efficient manner so that device parametervariations can be simulated to a level of 5σ and beyond.

SUMMARY OF THE INVENTION

The objective of improving SRAM cell performance over process variationsand environmental conditions are achieved by methods that analyze SRAMcell performance for one or multiple cell designs, predict yields withrespect to performance variables and the optionally and iterativelyadjust cell design parameters to optimize performance and yield.

The methods may be embodied in program instructions executing within aworkstation computer and also in a computer program product comprisingmedia for storing the program instructions for execution within aworkstation computer system.

One aspect of the invention represents an improvement over traditionalmemory cell modeling, as multiple statistical analyses are performed ononly a subset of circuit parameters for each of several performancevariables, while other parameters are fixed. The subset of circuitparameters are also varied systematically over the multiple analyses sothat sensitivities can be determined. The results of the statisticalanalyses are used to compute sensitivities of the performance variablesto the cell parameters and the cell parameters and/or operatingconditions are adjusted in conformity with the sensitivities in order toimprove the memory cell design.

An initial pass of the analysis may be performed with a statisticalanalysis with respect to the entire set of circuit parameters anddevices, in order to determine an initial set of sensitivities.Examination of the sensitivities (e.g., comparison of the sensitivitiesto a threshold value) is then used to eliminate devices/parameters fromthe subsequent analyses.

Because of the above-described technique, it is possible to extend theanalysis beyond a traditional analysis that would extend to only 3σ(three standard deviations) to a level of 5σ and beyond for at leastsome of the parameters, increasing device yields. The increase inanalysis speed (i.e., reduction in processing power requirements) makesit possible, for example, to extend an analysis to a level of 6σ or 7σ.Since the cells are not modeled over every device parameter, but onlythe parameters critical to the particular performance variable beingmodeled, computation time is reduced and sensitivities can be moreeffectively determined.

Another aspect of the invention provides for selecting a best celldesign or cell order by simultaneously modeling several cell designs,whereby the yield and yield distribution of performance variables can becompared and optimized for selecting the best cell design for a givenrange of environmental conditions and process variable statistics.

The foregoing and other objectives, features, and advantages of theinvention will be apparent from the following, more particular,description of the preferred embodiment of the invention, as illustratedin the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objectives, and advantages thereof,will best be understood by reference to the following detaileddescription of an illustrative embodiment when read in conjunction withthe accompanying drawings, wherein like reference numerals indicate likecomponents, and:

FIG. 1 is a schematic diagram of a memory cell that can be modeled inaccordance with an embodiment of the invention.

FIG. 2 is a flowchart depicting a method in accordance with anembodiment of the present invention.

FIG. 3 is a flowchart depicting a method in accordance with anotherembodiment of the present invention.

FIG. 4 is a pictorial diagram depicting a workstation computer system inwhich the methods of FIGS. 2 and 3 can be practiced by executing programinstructions of a computer program product in accordance with anembodiment of the present invention.

FIGS. 5A, 5B and 6-7 are bar graphs depicting results of analysesperformed in accordance with embodiments of the present invention.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENT

With reference now to the figures, and in particular with reference toFIG. 1, a memory cell that can be modeled by a method in accordance withan embodiment of the invention is shown. Transistors P10, N10, P11 andN11 form a cross-coupled static latch that provides the storage of avalue in the cell. Transistors N12 and N13 provide for access to thevalue in response to a wordline select signal WL. Bitlines BLT (truebitline) and BLC (complement bitline) couple all cells in a column, sothat when a row is selected by signal WL, only one row cell from eachcolumn is exposed to the memory logic. For a write operation, bitlinesBLC and BLT are charged to voltages corresponding to the desired stateof the memory cell and WL is activated (pulsed), setting the state ofthe latch formed by transistors P10, N10, P11 and N11. For a readoperation, the bitlines BLC and BLT are previously charged to oppositestate predetermined voltages (generally V_(dd) and ground), and tocommence the read, WL is pulsed and a sense amplifier coupled tobitlines BLC and BLT determines the stored state by differentialcomparison of bitlines BLC and BLT.

The two different operations detailed above are impacted in differentways by variations in the parameters of transistors P10-11 and N10-13.The variations lead to unstable (potentially erroneous) read and writeoperations when the variations rise above a certain level. As operatingfrequencies are increased and device sizes correspondingly decreased,the variations take on a statistically significantly greater rangecausing failure of an increasing number of devices in a lot. The presentinvention is directed toward an efficient method for statisticallyanalyzing the design of memory cells so that yields may be improved byselecting nominal values for the device parameters and environmentaloperating ranges or optimum operating points (such as power supplyvoltage ranges, power supply optimum value or temperature ranges) can bedetermined for a specific design. The analysis is performed on subsetsof devices within the memory cell for each performance variable beingevaluated. Multiple Monte-Carlo analyses are performed with systematicvariations in the parameters in the subset for each performancevariable, so that sensitivities of the performance variables to theassociated parameters can be obtained. The systematic variations can beperformed directly by adjusting the mean value input to each parameter(i.e., the nominal design value of the parameter such as the design VTvalue for a particular transistor).

The subsets of devices can be selected in advance by foreknowledge ofthe devices critical to a given performance variable, or an initial passof Monte-Carlo analyses can be performed on the entire cell to determinethe critical devices by the level of sensitivity of a performancevariable to the parameters of the critical devices. Parameters (andentire devices) for which the sensitivity falls below a threshold can beeliminated from subsequent iterations by fixing rather than varyingthose parameters. The result is a reduction in processing time andmemory requirements for subsequent iterations.

In particular, with respect to the memory cell depicted in FIG. 1, whenthe stored value is a logical “0” (with respect to the bitline values),the common channel connection of transistors P10 and N10 is near V_(dd).When a logical “1” is written to the cell, if transistors N12 and N10are “weak” (i.e., high resistance) and/or transistor P10 is “strong”(i.e., low resistance) the write operation can fail to change the stateof the memory cell. For a read operation, if transistor N11 is weak andtransistors P11 and/or N13 are strong, a read operation may change thestate of the cell. When the value stored in the memory cell is a logical“1”, the critical transistor sets are reversed, with variations intransistors N12, N10 and P10 causing potential failure of the writeoperation and variations transistors N11, N13 and P11 causing potentialfailure of the read operation. However, since the design and process aresymmetrical, it is not necessary to analyze both conditions. While thedevices themselves will not be symmetrical, the statistical analysisapplies to both conditions, because the statistics of the devices, e.g.the nominal design values and ranges should be the same.

Because of the above determination that certain devices are critical tocertain operations, the device parameters: V_(th) (transistor thresholdvoltage), W (channel width) and L (channel length) can be statisticallysimulated for just those devices for a particular performance variablesuch as read stability, write stability, read and write delays or noiseon internal cell nodes.

By reducing the amount of analysis that must be performed to determinewhether or not a memory cell design will fall below a certain yield, twogoals are accomplished: the amount of computation time required ismanaged; and greater separation of particular device parametervariations with respect to the variation of performance variablesbecomes possible. By separating the device parameter variations, nominalvalues of the device parameters can be more effectively determined andtraded-off and other factors such as environmental ranges or nominaloperating points can be determined.

While the illustrated cell is an example of a cell of order 4 that maybe analyzed and improved by a method according to an embodiment of theinvention, it should be understood that the techniques illustratedherein may be applied to memory cells of any order. (Order as usedherein refers to the number of devices that implement the storageelement of the cell exclusive of the bitline buffer transistors.)

Further, the present invention can be used to obtain information aboutwhat device parameters are more critical to performance variablestability by performing a sensitivity analysis on the results of thestatistical simulations. For example, power consumption can be reducedby studying leakage effects in subsets of devices within the cell anddetermining the sensitivity of leakage current to the various deviceparameters for the subset.

Also, the present invention can be used to analyze the yield for one ormore cell designs based on the performance variable criteria, with orwithout iterating or changing the cell design. For example, cells ofdevice count {1, 2 . . . 8} and so on may be simultaneously analyzed inorder to select the best performance parameter yield for a given set ofenvironmental conditions and process variations.

Also, when optimizing the cell designs by changing cell parameters, thedetermined cell parameter to performance variable sensitivities can beused to alter not only the mean values of the performance variabledistributions, but the performance variable distributions can be forcedto asymmetrical distributions (having a higher overall device count onthe desired side of a performance criteria) in order to improve yield.

Referring now to FIG. 2, a method in accordance with an embodiment ofthe present invention is depicted. First, subsets of devices for eachperformance variable to be studied are determined (step 50) and thenmultiple statistical simulations (e.g., Monte-Carlo analyses) areperformed over the systematic variations of parameters studied for thedevices in the subset (step 52). The subsets can be selected byintelligent observation such as the cell analysis described above thatdetermined the particular devices affecting particular performancevariables by observing operation of the circuit. Alternatively, a firstpass of step 52 may be made where all of the devices' parameters areunconstrained (i.e., the first subset is the set of all deviceparameters) and then after determining sensitivities of the performancevariables to the device parameters below in step 54, the subsets ofdevices for the first “improved” pass are selected as those devices foreach performance variable for which the sensitivities are high.

Next, the sensitivity of each performance variable to the systematicparameter variations (parameter input statistics variation) for thesubset associated with the performance variable is determined bydetermining the partial derivative of the performance variable withrespect to the parameter variations (step 54) and for an iterativetechnique, a check can be made if performance is at desired levels(decision 56) (or other suitable check such as convergence at a fixedvalue) and if the check determines that further computation is desirableor required, the parameters in each subset can be adjusted in conformitywith the determined sensitivities (step 58) and steps 50-56 are thenrepeated until decision 56 indicates termination of the process. Also,as indicated in the flowchart in step 58, some parameters can be fixedduring iteration (and/or some devices can be removed from subsets, i.e.,all of their parameters become fixed) when the sensitivity of particularperformance variables to parameter variations (or the parametervariations for an entire device) is below a threshold.

Referring now to FIG. 3, a method in accordance with another embodimentof the present invention is illustrated in a flowchart. The illustratedmethod may be combined with the techniques illustrated in FIG. 2, or maybe used alone. First, a memory cell model with multiple differing cellcircuits (e.g., cells of device count 1 to N) is built in the input tothe Monte-Carlo analyses (step 60). Then the model is simulated oversubset parameter variations and environmental conditions (step 62). Thesensitivities of each cell to the process parameters are then determined(step 64) and optionally, the process may be iterated in conformity withthe sensitivity results (step 66), until the yield distribution isoptimized for each cell (decision 66). At this point, the cell designscan be compared for yield of the performance variables and a cell designselected for further optimization (step 67) which may be performed bythe method illustrated in FIG. 2.

Referring now to FIG. 4, a workstation computer system, in which methodsaccording to an embodiment of the present invention are performed, isdepicted. A workstation computer 112, having a processor 116 coupled toa memory 117, for executing program instructions from memory 117,wherein the program instructions include program instructions forexecuting one or more methods in accordance with an embodiment of thepresent invention, such as the method described above with respect toFIG. 2.

Workstation computer 112 is coupled to a graphical display 113 fordisplaying program output such as simulation results and circuit layoutstructure input, design and verification programs implementingembodiments of the present invention. Workstation computer 112 isfurther coupled to input devices such as a mouse 115 and a keyboard 114for receiving user input. Workstation computer may be coupled to apublic network such as the Internet, or may be a private network such asthe various “intra-nets” and software containing program instructionsembodying methods in accordance with embodiments of the presentinvention may be located on remote computers or locally withinworkstation computer 112.

Referring now to FIG. 5, a graph depicting results of a method inaccordance with an embodiment of the invention is shown. The graphdepicts a Read Stability analysis result, where a Monte Carlo analysisof a cell output pass transistor such as N13 of FIG. 1 and half of thecross-coupled latch (transistors P1 and N11) were given statistics fordimensional variation (L,W) and threshold voltage variation. Movingacross the graph from left to right, an integer change by standarddeviation of threshold voltage is shown and within each change inthreshold voltage variation, each bar represents an integer change indimensional variation by standard deviation. All parameters were studiedto the 5σ level.

The study was made across a supply voltage range of 0.45V to 2.25V andthe dark portions of the bars indicate ranges where the read operationis stable. The following observations can be made: with only a variationin V_(th), the memory cell is unstable for supply voltages under 0.9V.When both dimensional and V_(th) variations are considered, a 4σvariation of the dimensions is tolerable up to a 3σ variation inthreshold voltage.

Using the sensitivity results depicted in FIG. 5 iteration can be madeas to process control (changing the input statistics) of the deviceparameters or nominal design values for the transistors in order toachieve a desired environmental range (such as supply voltage) or toextend the allowable deviation of device variations. Changes in thesensitivity results at each iteration can then be used to detect minimaof the sensitivities versus changes in the nominal design parameters orprocess controls.

Referring now to FIGS. 6A and 6B, results of another analysis inaccordance with an embodiment of the present invention is illustrated.FIG. 6A depicts a write delay distribution 72 and total failure count 70(i.e., the sample count for cell parameters and conditions where thestate of the cell never changed in response to a write operation). FIG.6B shows a read delay distribution 74. By determining the sensitivitiesof the distributions (e.g., sensitivities of the performance variablemean, standard deviation and skew of the distribution to one side of themean or the other), fixed parameters and mean values of variedparameters (i.e., those in the selected subsets) can be adjusted tochange the shape and position of the distribution in order to improveperformance and/or yield.

Referring now to FIG. 7, results of yet another analysis in accordancewith an embodiment of the invention is depicted. Two distributions areshown for voltage noise on the internal storage node of a cell. Voltagenoise on the storage node or other indicates cell instability in that anexcessive excursion leads to a change of cell state. In theillustration, two distributions 80 and 82 are shown corresponding tovoltage noise level distribution across quantities of two differentcells with differing device counts. Each cell can be optimized accordingto the above-described iterative process, or one pass can be made andthe cell design with the more desirable distribution (e.g., distribution80) is selected and further optimized.

While the invention has been particularly shown and described withreference to the preferred embodiment thereof, it will be understood bythose skilled in the art that the foregoing and other changes in form,and details may be made therein without departing from the spirit andscope of the invention.

1. A method for improving a design of a memory cell, comprising:selecting particular associated subsets of memory cell circuitparameters for each of a plurality of operational performance variables;determining statistics for each memory cell circuit parameter withinsaid unique subsets for simulation; statistically simulating each ofsaid operational performance variables over systematic variations ofeach memory cell circuit parameter in said associated subset for eachsimulated operational performance variable; computing sensitivities ofeach of said operational performance variables to said variations ofsaid memory cell circuit parameters within said associated subset. 2.The method of claim 1, wherein said selecting is performed by:performing multiple statistical analyses of a full set of devices withinsaid memory cell over variations of circuit parameters for said full setof devices; computing sensitivities of each of said operationalperformance variables to said variations of said memory cell circuitparameters within said full set of devices; and comparing saidsensitivities for each of said operational performance variables to athreshold criteria to select said associated subsets of parameters asthose parameters for which an associated operational performancevariable has a higher sensitivity.
 3. The method of claim 2, furthercomprising performing said multiple statistical analyses, said computingand comparing on multiple cell designs of differing order and furthercomprising selecting one or more of said multiple cell designs forfurther analysis by determining which of said multiple cell designs havelower values of said sensitivities.
 4. The method of claim 1, furthercomprising performing said selecting, determining, simulating andcomputing on multiple cell designs of differing order and furthercomprising selecting one or more of said multiple cell designs forfurther analysis by determining which of said multiple cell designs havelower values of said sensitivities.
 5. The method of claim 1, furthercomprising adjusting one or values within associated subsets inconformity with a result of said computing for each of said operationalperformance variables, whereby design of said memory cell is improved.6. The method of claim 1, further comprising: eliminating one or moreparameters from one or more of said subsets in conformity with a resultof said computing; and repeating said determining, simulating andcomputing, wherein said repetition is performed on said one or moresubsets having a reduced number of parameters.
 7. The method of claim 1,wherein said plurality of performance variables includes write stabilityand read stability, and wherein said simulating simulates said memorycell for each of write stability, write delay, read stability and readdelay over said associated subset.
 8. A workstation computer systemcomprising a processor for executing program instructions and a memorycoupled to said processor for storing program instructions, said programinstructions including program instructions for altering designparameters of a memory cell, said program instructions comprisingprogram instructions for: selecting particular associated subsets ofmemory cell circuit parameters for each of a plurality of operationalperformance variables; determining statistics for each memory cellcircuit parameter within said unique subsets for simulation;statistically simulating each of said operational performance variablesover systematic variations of each memory cell circuit parameter in saidassociated subset for each simulated operational performance variable;computing sensitivities of each of said operational performancevariables to said variations of said memory cell circuit parameterswithin said associated subset.
 9. The workstation computer system ofclaim 8, wherein said program instructions for selecting furthercomprise program instructions for: performing multiple statisticalanalyses of a full set of devices within said memory cell overvariations of circuit parameters for said full set of devices; computingsensitivities of each of said operational performance variables to saidvariations of said memory cell circuit parameters within said full setof devices; and comparing said sensitivities for each of saidoperational performance variables to a threshold criteria to select saidassociated subsets of parameters as those parameters for which anassociated operational performance variable has a higher sensitivity.10. The workstation computer system of claim 9, wherein said programinstructions for performing said multiple statistical analyses, saidcomputing and comparing are executed for multiple cell designs ofdiffering order and further comprising program instructions forselecting one or more of said multiple cell designs for further analysisby determining which of said multiple cell designs have lower values ofsaid sensitivities.
 11. The workstation computer system of claim 8,wherein said program instructions for selecting, determining, simulatingand computing are executed for multiple cell designs of differing orderand further comprising program instructions for selecting one or more ofsaid multiple cell designs for further analysis by determining which ofsaid multiple cell designs have lower values of said sensitivities. 12.The workstation computer system of claim 8, further comprising programinstructions for adjusting one or values within associated subsets inconformity with a result of said computing for each of said operationalperformance variables, whereby design of said memory cell is improved.13. The workstation computer system of claim 8, further comprisingprogram instructions for: eliminating one or more parameters from one ormore of said subsets in conformity with a result of said computing; andrepeatedly executing said program instructions for determining,simulating and computing, wherein said repetition is performed on saidone or more subsets having a reduced number of parameters.
 14. Theworkstation computer system of claim 8, wherein said plurality ofperformance variables includes write stability and read stability, andwherein said program instructions for simulating simulate said memorycell for each of write stability, write delay, read stability and readdelay over said associated subset.
 15. A computer program productcomprising media encoding program instructions for execution on aworkstation computer, said program instructions for altering designparameters of a memory cell, said program instructions comprisingprogram instructions for: selecting particular associated subsets ofmemory cell circuit parameters for each of a plurality of operationalperformance variables; determining statistics for each memory cellcircuit parameter within said unique subsets for simulation;statistically simulating each of said operational performance variablesover systematic variations of each memory cell circuit parameter in saidassociated subset for each simulated operational performance variable;computing sensitivities of each of said operational performancevariables to said variations of said memory cell circuit parameterswithin said associated subset.
 16. The computer program product of claim15, wherein said program instructions for selecting further compriseprogram instructions for: performing multiple statistical analyses of afull set of devices within said memory cell over variations of circuitparameters for said full set of devices; computing sensitivities of eachof said operational performance variables to said variations of saidmemory cell circuit parameters within said full set of devices; andcomparing said sensitivities for each of said operational performancevariables to a threshold criteria to select said associated subsets ofparameters as those parameters for which an associated operationalperformance variable has a higher sensitivity.
 17. The computer programproduct of claim 16, wherein said program instructions for performingsaid multiple statistical analyses, said computing and comparing areexecuted for multiple cell designs of differing order and furthercomprising program instructions for selecting one or more of saidmultiple cell designs for further analysis by determining which of saidmultiple cell designs have lower values of said sensitivities.
 18. Thecomputer program product of claim 15, wherein said program instructionsfor selecting, determining, simulating and computing are executed formultiple cell designs of differing order and further comprising programinstructions for selecting one or more of said multiple cell designs forfurther analysis by determining which of said multiple cell designs havelower values of said sensitivities.
 19. The computer program product ofclaim 15, further comprising program instructions for adjusting one orvalues within associated subsets in conformity with a result of saidcomputing for each of said operational performance variables, wherebydesign of said memory cell is improved.
 20. The computer program productof claim 15, further comprising program instructions for: eliminatingone or more parameters from one or more of said subsets in conformitywith a result of said computing; and repeatedly executing said programinstructions for determining, simulating and computing, wherein saidrepetition is performed on said one or more subsets having a reducednumber of parameters.